Intel delays Broadwell announcement date until 2014 because of defect concentration issues



 Intel declared yesterday that the introduction of its next-generation chips, codenamed Broadwell, are delayed. the company demoed the 14nm processors at idf last month, and claims that the new chip will cut power consumption an additional 30 minutes below the reductions we saw with Haswell due to the move to 14nm process technology, depressed from 22nm. Broadwell is also set to be significantly smaller than Haswell — sufficiently small to suit into tablets and type factors without requiring a disciple, and purportedly incorporating a GPU that pushes performance up an additional four-hundredth 
over the current generation.
During its Q3 telephone call, Intel ceo Brian Krzanich noted that the problems facing Broadwell are technical (as critical marketing related), language “It was simply a defect density issue.” The imperfection will begin production in the half-moon of the year. Intel claims that it’s “comfortable” with yields, however is still baking in fixes and changes to the core to higher improve its standing. this is unsurprising — however what Intel dismisses as “just a defect density” topic is, in fact, profoundly at the center of the issues facing trendy semiconductor manufacturing.
How defect densities wreck price curves
As semiconductor nodes shrink, the issue of building ever-smaller semiconductor device layouts becomes increasingly acute. The shift to dual-patterning will increase defect densities on its own, the elemental limitations of 192nm lithography are a continuing pressure, and also the got to ensure ever-higher levels of control over dopant distribution and voltage characteristics are slamming up against the elemental limits of physical laws. Defect compactness is a metric that refers to what number defects are possible to be gift per wafer of CPUs.
It’s important to grasp that defects aren’t binary. Fries don’t just work or not work. A chip may work dead however consume a lot of power than supposed. Imperfect dopant distribution or nanometer-size errors in semiconductor device placement will cause issues related to frequency scaling. the problem with low-power, inexpensive cores is that the manufacturer needs to tightly control both binary work don’t work defects and smaller issues that don’t destroy the processor, however stop it from hitting power targets.
One way of lowering the impact of defects is to build redundant circuit paths within the processor itself. All manufacturers integrate a degree of redundancy, however once manufacturing tolerances are being tightly squeezed, adding redundant circuits additionally pushes up complexity. A balance must be fastidiously struck to make sure that the evaluation and duplicate structures don’t end up intensifying the problem.
Consider the impact of defects that cumulatively increase electronic equipment TDP by 500th. A 50W-75W desktop chip now includes a TDP of 75W-112W — well within the cooling capabilities of a contemporary tower. A 17W laptop computer cut +50% TDP will match into any chassis capable of handling a 25W TDP. however a pill chip, already borderline at 5W, could also be pushed out of the house altogether if it hits the 7.5W mark. With Intel fighting exhausting to shake the perception of x86 chips as too power-hungry to suit into ARM-competitive type factors, it’s imperative that every generation of x86 processor deliver dividends on this front, though it costs top-end recital, as it did with Haswell.
All the goals be, however the chips have to be compelled to be yielding optimally to drop them into place.
Expect similar announcements in years to derive
Intel’s troubles during this area ought to be considered a bellwether for the business. It’s not that corporations will stop advancing, however that the rate of next-generation ramps is going to slow as manufacturers struggle to ramp merchandise through associate progressively uncooperative chain. From dangerous ultraviolet lithography to the 450mm wafer transition, a number of the best engineers on the world try to build instrumentation that may continue scaling, at the same time as the price per sq. mm of silicon increases at 20nm for the first give, forever.
With GlobalFoundries and TSMC still ramping 20nm, Intel’s 14nm interruption shouldn’t impact the company’s roadmaps or the lead its detached over its contestants. TSMC is waged to ramp 20nm and 16nm FinFETs at the same time, with the previous debuting in 2014 and also the latter launching in the 2016 timeframe. GlobalFoundries, Samsung, and IBM are assertive ahead with plans for a hybrid 14-20nm process, within which chips would marry 14nm front-end manufacturing with 20nm interconnects. The result (if it works), would be a chip with 14nm-style power consumption and performance, however 20nm size.
GlobalFoundries hasn’t issued firm steering on once it expects to begin ramping 20nm, however 2014 is the generally accepted date, with the 14nm technology coming back on 1-2 years thenceforth likewise. In both cases, slowdowns and delays might impact customers or the foundries themselves — not as a result of any inherent flaw, however because the scaling has become thus tough. Moore’s law’s long prognosis could also be gloomy, however there are still choices for boosting enthusiast performance.

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